Samsung Electronics' semiconductor division is accelerating capacity expansion to meet the demand for advanced logic and memory semiconductor production amid the AI boom. Its 2nm wafer fab in Taylor, Texas, USA, has entered trial operations, with EUV lithography machine testing initiated and key equipment being introduced in phases to prepare for initial operations this year and full-scale production in 2027. In late March, Samsung placed bulk front-end equipment orders for the PH2 and PH4 phases of its Pyeongtaek P4 wafer fab cluster, which will produce 1c nm DRAM Die supporting HBM4. Currently, investment in PH1 has been completed, and equipment installation in PH3 is nearly finished, with an expected wafer input volume of 13-14K WPM this year. Equipment introduction for PH4 is planned for May-June this year, while PH2 has commenced cleanroom construction, with equipment installation expected in November this year and completion in February 2027.