At the recently held ISSCC 2026 conference, the Belgian research center imec (Interuniversity Microelectronics Centre) unveiled a 7-bit, 175GS/s analog-to-digital converter (ADC). The chip, fabricated using a 5-nanometer FinFET process, features a core area of just 250×250 square micrometers and achieves an energy consumption as low as 2.2 picojoules per conversion sample, with a sampling rate that ranks among the highest globally. This chip can meet the growing throughput and processing demands of data centers driven by AI and cloud computing, avoiding the common issues of soaring chip area and power consumption associated with ultra-high-speed sampling rates. Its breakthroughs lie in two patented technologies: first, a novel linearization technique that effectively corrects distortion through ramp signal shaping; second, a switched input buffer technology that efficiently drives the ADC's 2048-channel time-interleaved array, ensuring signal integrity. imec is now developing a next-generation 3-nanometer process design based on this achievement and exploring design options at the 1.4-nanometer level.