Recently, the EICAS research team from the College of Integrated Circuits and the MIIT Key Laboratory of 'Aerospace Integrated Circuits and Microsystems' at Nanjing University of Aeronautics and Astronautics has achieved a notable milestone in the realm of lattice-based post-quantum cryptography chip design. Their research zeroes in on the hardware realization and performance appraisal of a high-efficiency number-theoretic transform (NTT) accelerator leveraging RRAM compute-in-memory (CIM) technology. The pertinent accomplishments, encapsulated in the paper titled 'DRR-NTT: Efficient NTT Accelerator in Lattice-Based Cryptography By Dimensionality Reduction in RRAM,' have garnered acceptance from The Workshop on Cryptographic Hardware and Embedded Systems (CHES), a premier international conference hosted by the International Association for Cryptologic Research, dedicated to cryptography. The research crew employed dimensionality reduction techniques to fine-tune the RRAM array architecture, leading to a substantial reduction in both the hardware overhead and energy consumption associated with NTT operations. This breakthrough offers an inventive approach to the design of specialized chips tailored for post-quantum cryptography algorithms. The achievements boast considerable practical significance in the domain of cryptographic chips that can withstand quantum computing threats, signifying that China has ascended to the global vanguard in terms of compute-in-memory chip architecture and the hardware implementation of post-quantum cryptography.