During CES 2026, AMD took the stage to present the world's inaugural next-generation Zen6 EPYC Venice processor, which leverages TSMC's cutting-edge 2nm manufacturing process. Recently, a deeper dive into its architectural specifics has surfaced, highlighting that the Zen 6C architecture variant can soar up to an impressive 256 cores. This feat is accomplished through the utilization of higher-density Core Chiplet Dies (CCDs) and a groundbreaking dual Input/Output Die (IO Die) architecture.

Each Zen 6C CCD packs a staggering 32 physical cores, marking a significant leap by doubling the core count from its predecessor. Concurrently, the footprint of a single CCD has expanded to roughly 155mm². The fully-loaded Venice processor comes armed with 8 CCDs, culminating in a total of 256 cores and a substantial 1024MB (or 1GB) of L3 cache. Moreover, Venice has also elevated its IO Die architecture to new heights, incorporating two IO Dies built on TSMC's N6 process. These IO Dies collectively span an IO area of up to 750mm², seamlessly integrating essential IP modules such as memory and PCIe controllers, alongside AI acceleration units.