By 2025, TSMC’s production lines dedicated to advanced packaging technologies, including CoWoS, will find themselves inundated with orders. This will push their production capacity to its limits, making it challenging for TSMC to independently accommodate the burgeoning demand from AI chip customers. Amid a surge in multi-chiplet packaging solutions adoption by key clients such as NVIDIA, AMD, Apple, Google, Qualcomm, and MediaTek, this capacity constraint has emerged as a critical issue for the entire AI industry ecosystem.

To address this pressing demand, TSMC is taking a two-pronged approach. On one hand, it is ramping up its CoWoS production lines both in Taiwan and the United States. On the other hand, it is outsourcing a portion of its orders to local Taiwanese packaging and testing companies, including ASE Group and SPIL. Meanwhile, Intel is capitalizing on its cutting-edge packaging technologies, such as EMIB and Foveros, to lure manufacturers like Apple and Qualcomm to consider it as an alternative supplier. This move aims to help these companies diversify their supply chain risks.

Google has already announced its intention to trial Intel’s EMIB packaging technology in its upcoming TPU v9 chip, slated for release in 2027. Additionally, Meta has commenced evaluating this technology for its MTIA products. TSMC’s capacity crisis is spurring the diversification of the advanced packaging supply chain, signaling that the days of a single manufacturer dominating the market are unlikely to make a comeback.