On November 8, IT Home reported that the latest GCC compiler patch, which was merged on November 7 (local time), inadvertently revealed the core Instruction Set Architecture (ISA) of AMD's upcoming next-generation Zen 6 processor. This architecture is poised to introduce a host of extensions tailored for High-Performance Computing (HPC) and Artificial Intelligence (AI), encompassing AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and VNNI INT8.

Among these enhancements, AVX512 FP16 is set to bolster floating-point computing prowess, providing a significant boost to AI inference tasks and high-performance scientific computations. Meanwhile, VNNI INT8 is designed to elevate the efficiency of low-precision integer matrix operations, thereby expediting the execution of deep learning models.

The Zen 6 architecture will also debut two server product line variants: Classic and Dense. The Dense variant, in particular, will boast up to 256 cores, with each Core Complex (CCX) housing 128MB of L3 cache, culminating in a total L3 cache capacity of up to 1024MB.

For client products, the Zen 6 architecture will cater to at least four major series, including models such as 'Olympic Ridge' for the high-end AM5 platform. It is anticipated that multi-chip design models will leverage TSMC's N2P process, while single-chip designs like Medusa Point and Gator Range APU are projected to utilize TSMC's N3P or N3C processes.

AMD has scheduled a preview of Zen 6-related content at its Financial Analyst Day, with an official launch expected to take place during CES 2026.