Data sourced from Tianyancha reveals that on September 26, 2025, Shanghai Excelliance MOS Co., Ltd. was officially granted an invention patent. The patent, named "Device Structure Fabrication Method of SGT MOSFET," carries the application number CN202411442909.2 and was filed on October 15, 2024.

This particular patent outlines a method that entails the sequential formation of a first thermal oxide layer, an isolation layer, and a trench oxide layer on both the surface of an epitaxial layer and the sidewall of a first recess. Subsequently, based on the specified thickness requirements for the oxide layer on the trench sidewall, the thickness of the first thermal oxide layer is carefully reduced. This reduction serves a dual purpose: it minimizes the consumption of the epitaxial layer and, as a result, significantly enhances the voltage tolerance of the SGT MOSFET.

Moreover, the integration of an isolation layer into the process enables the creation of an inter-gate oxide layer on the protruding surface of the first polysilicon layer with the desired thickness. This precise control over the oxide layer thickness leads to a reduction in the gate-source capacitance of the SGT MOSFET, a key performance metric.

Since the dawn of the current year, Excelliance MOS has achieved a remarkable feat by securing 14 new patent authorizations. This figure represents a substantial 133.33% increase compared to the same period in the previous year, underscoring the company's commitment to innovation and technological advancement.