AMD is set to roll out a cutting - edge D2D interconnect technology in its upcoming Zen 6 processors. This technology will take the place of the SERDES PHY solution, which has been a staple since the Zen 2 architecture era. At present, this technological overhaul has already undergone successful validation on the Strix Halo APU. The results are remarkable, showcasing substantial enhancements in both energy efficiency and the optimization of communication latency.

The Strix Halo APU makes use of TSMC's InFO - oS packaging technology along with the redistribution layer (RDL) process. It adopts a 'massive wiring' strategy, arranging a vast number of fine parallel wires on the interposer. This arrangement creates wide parallel port communication channels. By doing so, it bids farewell to the traditional SERDES modules. Instead, it employs a rectangular array of micro - pads for direct data transmission. This enables data to be communicated directly without the need for the cumbersome serial - to - parallel conversion process.

This innovative design brings about multiple benefits. It effectively cuts down on power consumption and reduces latency. Moreover, it offers the flexibility to enhance bandwidth by simply increasing the number of ports. However, the new approach is not without its challenges. For instance, the multi - layer RDLs introduce a higher level of process complexity during design.

Despite these challenges, the industry as a whole is optimistic. It widely expects that the interconnect concept, which has been validated by the Strix Halo, will be fully implemented in the Zen 6 processors. This implementation is anticipated to inject fresh vitality into the delicate balance between processor energy efficiency and performance.