Combinatorial optimization and probabilistic reasoning are ubiquitous across various domains, including artificial intelligence, electronic design automation, communication networks, and logistics planning. Boolean satisfiability (SAT) stands out as a prime example of such challenges. Traditional von Neumann architectures frequently face performance and energy efficiency constraints when addressing these issues, primarily due to extensive data movement, sequential processing, and the substantial costs associated with training. As problem complexity grows, the limitations of current general-purpose processors in terms of energy efficiency, parallel processing capabilities, and scalability become increasingly pronounced. Consequently, there is a burgeoning interest in transitioning computational tasks from the software realm to the hardware level, harnessing the inherent physical properties of devices to enable direct sampling and optimization. This approach represents a highly promising avenue for future research.