Insiders with knowledge of the situation disclose that TSMC is in the process of developing an innovative chip packaging technology, known as CoPoS (Chip-on-Panel-on-Substrate). This groundbreaking approach embodies the principle of 'converting circles into squares,' substituting the conventional circular silicon interposers with square substrates crafted from glass or sapphire. Leveraging rectangular panel substrates (such as 310x310mm, 750x620mm), it boosts the utilization efficiency of the packaging area to a remarkable 81% to 95%, a substantial improvement over the traditional 300mm circular wafers. The goal of CoPoS is to slash packaging costs per unit area by roughly 10% to 30%, while also facilitating the integration of a greater number of Chiplets and high-bandwidth memory, with a theoretical peak bandwidth projected to surpass 13-15TB/s. This technology is primarily aimed at applications including next-gen AI training/inference chips, high-performance computing chips, and 5G communication chips. TSMC's CoPoS pilot production line initiated equipment delivery in February 2026, with the complete production line slated for full establishment by June. Mass production is projected to kick off from late 2028 to the first half of 2029, with production facilities located at the Chiayi AP7 plant and the Arizona plant in the U.S. NVIDIA is poised to be the first customer, with AMD, Broadcom, and others also considered as potential customers.